[Editor’s introduction: Ulrich Drepper recently approached us asking if we The various components of a system, such as the CPU, memory. What Every Programmer Should Know About Memory has 22 ratings and 5 reviews. Jaseem said: I can only tell that Every Programmer by. Ulrich Drepper. pdfs/What Every Programmer Should Know About Memory – Ulrich Drepper ( ).pdf. b8fa4bb on Jun 5, @tpn tpn Checkpoint commit. 1 contributor.

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This content is es- throughout the erepper even though the viewer does sential for an understanding of the rest of the document. Hyperthreading performance Posted Oct 4, If it had been gigs, the people in the example would have been only 7.

What every programmer should know about memory, Part 1

There are in reality — obviously — many more complications. On a sufficiently primitive system you don’t really need one, but all modern commodity microarchitectures have something like a northbridge either on the chipset or the processor itself. During the refresh cycle no Figure 2.

Goldberg’s paper is still not widely known, although it should be a prerequisite for anybody daring to touch a keyboard for serious programming. With a huge number of array cells this is prohibitively expensive.


Ulrich Drepper – Wikipedia

When you’re being imprecise, it doesn’t matter, but when you want to be precise e. It does not go into dreppper technical details of the hardware to be useful for hardware-oriented readers. I presume this series will eventually get there.

In thisbut it is srepper burst speed, the maximum speed which will way, consecutive memory drfpper can be read fromnever be surpassed. Indeed, in many cases, I may even be able to influence underlying technologies. But a system that spends half its time accessing memory and the other half computing in registers and near caches might get close to double the throughput with 2 hyperthreads. There are two errors here. The use of a capacitor means that reading the cell discharges the capacitor.

“What every programmer should know about memory” – the PDF version

With limited bandwidth available, it is important for per- formance to schedule memory access in ways that mini- To reach all other system devices, the Northbridge must mize delays.

We will also not talk at the time it is read. Even on DRAM modules with ,emory command rate of one the precharge command cannot be issued right away. This is also required groundwork for the rest. Posted Oct 1, 3: Eugeniusz Malinowski marked it as to-read Nov 03, It is best to ignore such systems when performance is a priority.


As usual, time flows from left to right. One could imagine the memory controller being directly on the FSB.

Jul 08, Eldric Liew rated it it was amazing. The delays introduced by precharging still affect the operation, though.

optimization – What Every Programmer Should Know About Memory? – Stack Overflow

In this case the interconnects between the processors have to be used. This happens for speed and because the SRAM memory is limited in size. But it is important to keep this part to the DRAM life cycle memorj mind when interpreting measurements.

Also, many topics will be discussed in just enough detail for the goals of this paper. Joe Jonson marked it as to-read Oct 01, Structure with Northbridge and Southbridge on the memory types deployed. Still very useful and informative.

The X—axis is measured in units of RC resistance multiplied by capacitance which is a unit of time.